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DMA Operation with a FIFO Backend
DMA Operation with a FIFO Backend
Figure 6-38 shows a DMA Master transfer from a backend FIFO to the PCI bus. During the transfer, the Target asserts
STOPN, causing the Master to stop the transfer. During the first PCI cycle, the core reads data words 0 to 9 from the
backend but only transfers 0 to 4 on the PCI bus. During the second PCI cycle, the core reads data words 10 to 13 from
the backend, but transfers 5 to 9 on the PCI bus. These data words had been stored inside the core between data
transfers. Words 10 to 13 are stored inside the core and will be transferred during the next PCI cycle.
cycle
clk
framen
A0 A1 A2 A3
0 1 2 3 4 5 6 7 8 9 A0 A1 A2 A3 0 1 2 3 4 5 6 7 8 9 10 11 12
cben[3:0]
ad[31:0]
7
0
0
1 2 3 4 5
7
5
0
6 7 8 9 10 11
par
devseln
irdyn
trdyn
stopn
reqn
gntn
mast_active
dp_start
dp_done
bar_select[2:0]
0
7
0
rd_cyc
rd_stb_out
rd_stb_in
rd_sync
mem_data_in[31:0]
0 1 2 3 4 5 6 7 8 9
10 11 12 13
mem_add[11:0]
000
004 008 00C 010 014 018 01C 020 024
028
014
018 01C 020
Figure 6-38 · DMA Cycle with a FIFO Backend
v4.0
87
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